Bare electronic chips typically need to be tested. Frequently, the testing is done at a wafer level after the chips have been largely fabricated, but before the chips are diced apart and packaged. Such a test is often called a wafer test and sort operation, since good chips can be sorted from bad chips that fail the test, saving time and money since the bad chips are discarded (or re-worked) before the effort of packaging the chips.
Conventional test heads used buckling-beam and/or resilient-contact technologies for the contacting pins in the probe head. Long probe lead lengths are often needed to compensate for variability in probe lengths and bent probe leads, variability in the height of the balls or bumps of the circuit being tested, and to provide gentle contact force. Unfortunately, long power-supply wiring circuits, including long probe leads have larger inductances and resistances which result in relatively large voltage droops across the leads, particularly for power-supply leads that draw large currents. Such voltage droops result in slower test speeds, thus requiring larger tester fleets to test a given quantity of chips per unit time. This can be a substantial capital cost to the chip manufacturer.
Further, voltage droops can prevent a tester from performing its tests at full speed, thus preventing the detection of faulty chips that cannot run at full speed.
What is needed is a simple, inexpensive, reliable method and apparatus to test electronic chips, so that the tester is compact and includes locally situated circuitry to reduce voltage droops and improve voltage regulation and transient suppression.